CPU COre

(Virtually) Designed a CPU core based on a custom 24 bit version of MIPS assembly language.

Designed and built all parts:

-Pointer Counter with proper jumping and branching

-A register file with 8 16 bit registers

-An ALU (16 bit) with the following capabilities: Add, Subtract, Nor, Nand, Shift Left, and Shift Right

-A controller subcircuit that splits up the Instruction into control booleans to control the data flow

-Loadable dram and sram

-Very limited io access (display and keyboard input)